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ESMT
Mobile DDR SDRAM
M53D128168A
Operation Temperature Condition -40C~85C
2M x 16 Bit x 4 Banks
Mobile DDR SDRAM
Features
JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 Special function support PASR (Partial Array Self Refresh) Internal TCSR (Temperature Compensated Self Refresh) DS (Driver Strength) All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD/VDDQ = 1.7V ~ 1.9V Auto & Self refresh 15.6us refresh interval (64ms refresh period, 4K cycle) 1.8V LVCMOS-compatible inputs 60 ball BGA package
Ordering information :
Part NO. M53D128168A -7.5BAIG M53D128168A -10BAIG MAX FREQ 133MHz 100MHz VDD 1.8V PACKAGE 8x13 mm BGA COMMENTS Pb-free Pb-free
Functional Block Diagram
CLK CLK CKE Address
Mode Register & Extended Mode Register
Clock Generator
Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter
Bank A
DQS
Sense Amplifier
DM
CAS WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Column Address Buffer & Refresh Counter
Column Decoder
DQ
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Pin Arrangement 60 Ball BGA (8x13mm) TOP View
1 A B C D E F G H J K L M
VSSQ DQ14 DQ12 DQ10 DQ8 NC
M53D128168A
Operation Temperature Condition -40C~85C
2
DQ15 VDDQ VSSQ VDDQ VSSQ VSS CLK NC A11 A8 A6 A4
3
VSS DQ13 DQ11 DQ9
UDQS
7
VDD DQ2 DQ4 DQ6
LDQS
8
DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0
A10/AP
9
VDDQ DQ1 DQ3 DQ5 DQ7 NC
UDM CLK CKE A9 A7 A5 VSS
LDM WE
RAS BA1 A0 A2 VDD
A1 A3
Pin Description
Pin Name Function Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe. LDQS corresponds to the data on DQ0~DQ7; UDQS correspond to the data on DQ8~DQ15. Pin Name Function DM is an input mask signal for write data. LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~DQ15. Clock input Clock enable Chip select Supply Voltage for DQ Ground for DQ No connection
A0~A11, BA0,BA1
LDM, UDM
DQ0~DQ15 RAS CAS
WE
CLK, CLK CKE CS VDDQ VSSQ NC
VSS VDD LDQS, UDQS
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Absolute Maximum Rating
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Note : Symbol VIN, VOUT VDD VDDQ TSTG PD IOS
M53D128168A
Operation Temperature Condition -40C~85C
Value -0.5 ~ 2.7 -0.5 ~ 2.7 -0.5 ~ 2.7 -55 ~ +150 1.0 50
Unit V V V C W mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = -40 to 85 C ) Parameter Supply voltage I/O Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input Voltage Level, CLK and CLK inputs Input Differential Voltage, CLK and CLK inputs Input leakage current Output leakage current Notes: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK . . Symbol VDD VDDQ VIH (DC) VIL (DC) VOH (DC) VOL (DC) VIN (DC) VID (DC) II IOZ Min 1.7 1.7 0.7 x VDDQ -0.3 0.9 x VDDQ -0.3 0.4 x VDDQ -2 -5 Max 1.9 1.9 VDDQ + 0.3 0.3 x VDDQ 0.1 x VDDQ VDDQ + 0.3 VDDQ + 0.3 2 5 Unit V V V V V V V V 1 IOH = -0.1mA IOL = 0.1mA Note
A A
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DC CHARACTERISTICS
Recommended operating condition unless otherwise notedTA = -40 to 85 C Parameter Operating Current (One Bank Active) Symbol ICC0 ICC2P Precharge Standby Current in power-down mode Test Condition
M53D128168A
Operation Temperature Condition -40C~85C
Version -7.5 60 -10 50
Unit mA mA
tRC= tRC (min), tCK = tCK (min), CKE = High, /CS = High between valid commands, address inputs are switching, data input signals are stable All banks idle, CKE = Low, /CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable All banks idle, CKE = Low, /CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable All banks idle, CKE = Low, /CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable All banks idle, CKE = Low, CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable One bank active, CKE = Low, CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable One bank active, CKE = Low, CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable One bank active, CKE = Low, CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable One bank active, CKE = Low, CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable One bank active, BL=4, tCK = tCK (min), continuous read bursts, IOUT = 0 mA, address inputs are switching, 50% data changing each burst One bank active, BL=4, tCK = tCK (min), continuous write bursts, IOUT = 0 mA, address inputs are switching, 50% data changing each burst Burst refresh, tRC= tRC (min), tCK = tCK (min), CKE = High, address inputs are switching, data input signals are stable
0.5
ICC2PS
0.5
mA
Precharge Standby Current in non power-down mode
ICC2N
28
22
mA
ICC2NS
28
22
mA
ICC3P Active Standby Current in power-down mode ICC3PS
5
mA
2
Active Standby Current in non power-down mode (One Bank Active)
ICC3N
45
35
mA
ICC3NS
25
20
mA
Operating Current (Burst Mode)
ICC4R
90
75
mA
ICC4W
90
75
mA
Refresh Current
ICC5
75
60
mA
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Self Refresh Current ICC6 CKE = Low, CS = High, tck = tck (min), address & control & data inputs are stable 4 Banks 2 Bank 1 Bank Deep Power Down Current ICC7 address & control & data inputs are stable
M53D128168A
Operation Temperature Condition -40C~85C
TCSR range
15 340 290 240
45 360 310 260 10
70 380 320 280
85 400 350 300
C
uA
uA
Note: 1. It has +/- 5 C tolerance. 2. ICC specifications are tested after the device is properly intialized. 3. Definitions for ICC: LOW is defined as V IN 0.1 * V DDQ ; HIGH is defined as V IN 0.9 * V DDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification AC Operation Conditions
Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Input Crossing Point Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min 0.8 x VDDQ -0.3 0.6 x VDDQ 0.4 x VDDQ Max VDDQ+0.3 0.2 x VDDQ VDDQ+0.3 0.6 x VDDQ Unit V V V V 1 2 Note
Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Input / Output Capacitance
(VDD = 1.8V, VDDQ =1.8V, TA = 25 C , f = 1MHz) Parameter Input capacitance (A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data & DQS input/output capacitance Input capacitance (DM) Symbol CIN1 CIN2 COUT CIN3 Min 1.5 1.5 2.0 2.0 Max 3.0 3.5 4.5 4.5 Unit pF pF pF pF
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(VDD = 1.8V, VDDQ =1.8V, TA = 25 C , f = 1MHz)
Parameter Input signal minimum slew rate Input levels (VIH/VIL) Input timing measurement reference level Output timing measurement reference level Value 1.0
M53D128168A
Operation Temperature Condition -40C~85C
AC Operating Test Conditions (VDD = 1.7V~ 1.9V, TA = -40 C to 85 C )
Unit V/ns V V V
0.8 x VDDQ / 0.2 x VDDQ 0.5 x VDDQ 0.5 x VDDQ
AC Timing Parameter & Specifications (VDD = 1.7V~1.9V, VDDQ=1.7V~1.9V, TA =-40 C to 85 C )
Parameter
CL3 Clock Period CL2 Access time from CLK/ CLK CLK high-level width CLK low-level width Data strobe edge to clock edge Clock to first rising edge of DQS delay Data-in and DM setup time (to DQS) Data-in and DM hold time (to DQS) DQ and DM input pulse width (for each input) Input setup time (fast slew rate) Input hold time (fast slew rate) Input setup time (slow slew rate) Input hold time (slow slew rate) Control and Address input pulse width DQS input high pulse width DQS input low pulse width DQS falling edge to CLK rising-setup time DQS falling edge from CLK rising-hold time Data strobe edge to output data edge Data-out high-impedance window from CLK/ CLK Data-out low-impedance window from CLK/ CLK tCK tAC tCH tCL tDQSCK tDQSS tDS tDH tDIPW tIS tIH tIS tIH tIPW tDQSH tDQSL tDSS tDSH tDQSQ tHZ tLZ 2.0 1.3 2.0 1.5 3.0 0.4 0.4 0.2 0.2 1.0 Symbol -7.5 min 7.5 12 2 0.45 0.45 2 0.75 1.0 0.75 tDS + tDH 0.6 0.6 0.6 6.0 2.0 1.5 2.0 1.7 3.4 0.4 0.4 0.2 0.2 1.0 max 7 0.55 0.55 7 1.25 min 10 15 2 0.45 0.45 2 0.75 1.1 1.1 tDS + tDH 0.6 0.6 0.7 7.0 -10 max ns 9 0.55 0.55 9 1.25 ns tCK tCK ns tCK ns ns ns ns ns ns ns ns tCK tCK tCK tCK ns ns ns
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AC Timing Parameter & Specifications-continued
Parameter
Half Clock Period DQ-DQS output hold time Data hold skew factor ACTIVE to PRECHARGE command Row Cycle Time AUTO REFRESH Row Cycle Time ACTIVE to READ,WRITE delay PRECHARGE command period Minimum tCKE High/Low time ACTIVE bank A to ACTIVE bank B command Write recovery time Write data in to READ command delay Col. Address to Col. Address delay Average periodic refresh interval Write preamble Write postamble DQS read preamble DQS read postamble Clock to DQS write preamble setup time Load Mode Register / Extended Mode register cycle time Exit self refresh to first valid command Exit power-down mode to first valid command Autoprecharge write recovery+Precharge time Symbol tHP tQH tQHS tRAS tRC tRFC tRCD tRP tCKE tRRD tWR tWTR tCCD tREFI tWPRE tWPST tRPRE tRPST tWPRES tMRD tXSR tXP tDAL -7.5 min tCLmin or tCHmin tHPmin-tQHS 45 67.5 80 22.5 22.5 2 15 15 1 1 0.25 0.4 0.9 0.4 0 2 120 25 (tWR/tCK) + (tRP/tCK) 15.6 0.6 1.1 0.6 max 0.75 70K -
M53D128168A
Operation Temperature Condition -40C~85C
-10 min tCLmin or tCHmin tHPmin-tQHS 50 80 90 30 30 2 15 15 1 1 0.25 0.4 0.9 0.4 0 2 120 25 (tWR/tCK) + (tRP/tCK) 15.6 0.6 1.1 0.6 max 1.0 70K ns ns ns ns ns ns ns ns tCK ns tCK tCK tCK us tCK tCK tCK tCK ns tCK ns ns ns
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Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Self Refresh Entry Exit CKEn-1 CKEn CS H H H L H H X X H L H X X L L L L H L L RAS L L L H X L H CAS L L L H X H L
M53D128168A
Operation Temperature Condition -40C~85C
WE
DM X X X X X X
BA0,1
A10/AP OP CODE OP CODE X X
A11, A9~A0
Note 1,2 1,2 3 3 3 3 4 4 4 4,6
L L H H X H H
Bank Active & Row Addr. Read & Column Address Write & Column Address Deep Power Down Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Entry Exit Burst Stop Precharge Bank Selection All Banks Entry Exit Precharge Power Down Mode DM No Operation Command Entry Exit
V V
Row Address L H Column Address Column Address
H H L H H H L H L H H
X L H X X L H L H
L L H L L H L X H L H L H L
H H X H L X V X X H X V X X H
L H X H H X V X X H X V X H
L L X L L X V X X H X V X H
X X X X X X X X
V
L H X X
7 X 5
V X
L H X
Active Power Down
X X V X X X 8
X
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low) 1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto".. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
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Basic Functionality Power-Up and Initialization Sequence
M53D128168A
Operation Temperature Condition -40C~85C
The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) Apply VDD before or at the same time as VDDQ. 2. Start clock and maintain stable condition for a minimum. 3. The minimum of 200us after stable power and clock (CLK, CLK ),apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS.
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CKE
High level is necessary
CS
tRP
RAS
tRFC
tRFC
tMRD
tMRD
CAS
ADDR
Key
Key
RA
BA1
BS
BA0
BS
A10 /AP
RA
DQ
High-Z
WE
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Re fresh
Mode Register Set Row Active Extended Mode Register Set : Don't care
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Mode Register Definition Mode Register Set (MRS)
M53D128168A
Operation Temperature Condition -40C~85C
The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS latency, addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written in the power up sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1
BA0
A11~ A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
RFU*
CAS Latency
BT
Burst Length
Mode Register
A3 0 1
Burst Type Sequential Interleave
Burst Length CAS Latency BA1 BA0 0 0 1 0 Operating Mode MRS Cycle EMRS Cycle A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve Reserve Reserve A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Latency Sequential Interleave Reserve Reserve 2 2 4 4 8 8 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve
* RFU should stay "0" during MRS cycle
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Burst Length 2 Starting Address (A2, A1,A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6
M53D128168A
Operation Temperature Condition -40C~85C
Burst Address Ordering for Burst Length
Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
4
8
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Extended Mode Register Set (EMRS)
M53D128168A
Operation Temperature Condition -40C~85C
The extended mode register stores for selecting PASR and DS. The extended mode register set must be done before any active command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA1,low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more register). The state of address pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in the extended mode register. Refer to the table for specific codes. The extended mode register can be changed by using the same command and clock cycle requirements during operations as long as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks refreshed.
Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the three temperature range : 15C, 45C, 70C and 85C. 2. 3. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. It has +/-5C tolerance
BA1 BA0 1 0
A11 A10 A9 A8 A7 0 0 0 0 0
A6 A5 A4 A3 DS RFU*
A2 A1 A0 PASR
Address bus Extended Mode Register Set A2-A0 000 001 PASR 010 011 100 101 111 Self Refresh Coverage 4Bank 2 Bank (BankA& BankB) or (BA1=0) 1 Bank (BankA) or (BA0=BA1=0) R R R R
Internal TCSR A6-A5 00 01 10 11 Driver Strength Full Strength 1/2 Strength 1/4 Strength R Remark R : Reserved
DS
* RFU should stay "0" during EMRS cycle
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Precharge
M53D128168A
Operation Temperature Condition -40C~85C
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits A10/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE . For both Deselect and NOP, the device should finish the current operation when this command is issued.
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Row Active
M53D128168A
Operation Temperature Condition -40C~85C
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The Mobile DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
0 CLK CLK 1 2 3 4 5 6
Address
Bank A Row Addr. RAS-CAS delay (tRCD)
Bank A Col. Addr.
Bank B Row Addr.
Bank A Row. Ad dr.
RAS-RAS delay (tRRD) Write A with Auto Prec harge Bank B Activate NOP Bank A Activate
Command
Bank A Activate
NOP
NOP
ROW Cycle Time (tRC)
: Don't Care
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.
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Essential Functionality for Mobile DDR SDRAM Burst Read Operation
M53D128168A
Operation Temperature Condition -40C~85C
Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR SDRAM until the burst length is completed.

CLK CLK 0 1 2 3 4 5 6 7 8
COMMAND
READ A
NOP
NOP tDQSCK tRPRE
NOP
NOP
NOP
NOP
NOP
NOP
tRPST
DQS CAS Latency=3 DQ's tAC
Dout0 Dout1 Dout2 Dout3
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.
0 CLK CLK 1 2 3 4 5 6 7 8
CO MMA ND
NOP
W RITEA
NOP
WRITEB
NOP
NOP
NOP
NOP tWR
NOP
tDQSS(max) DQS tWPREH tWPRES DQ's
Din0 Din1 Din2 Din3 Din0 Din1 Din2 Din3
tDQSS(min) DQS tWPREH tWPRES DQ's
Din0 D in1 Din2 Din3 Din0 D in1 Din2 Din3
tWR
tDS tDH
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Read Interrupted by a Read
M53D128168A
Operation Temperature Condition -40C~85C
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.

0 CLK CLK tCCD(min) COMMAND READ A RE AD B NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8
DQS
Hi-Z
tDQSCK tRPRE tRPST
DQ's
Hi-Z
D o u t A0 D o u t A 1 D ou t B 0 D o u t B 1 D o u t B2 D o u t B 3
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ's(Output drivers) in a high impedance state. To insure the DQ's are tri-stated one cycle before the beginning the write operation, Burt stop command must be applied at least RU(CL) clocks RU means round up to the nearest integer before the Write command.
CLK CLK 0 1 2 3 4 5 6 7 8
COMMAND
READ
Burst Stop
NOP tDQSCK
NOP
NOP
W RITE tDQSS
NOP
NOP
NOP
DQS
tRPRE
tRPST
tWPREH tWPST Din 0 Din 1 Din 2 tWPRE Din 3
tAC DQ's
D ou t 0 D o u t 1
tW PRES
The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 16/46
ESMT
Read Interrupted by a Precharge
M53D128168A
Operation Temperature Condition -40C~85C
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.

CLK CLK 1tCK COMMAND READ
Precha rge
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK DQS tRPRE tAC DQ's
D ou t 0 D ou t 1 D o ut 2 D o ut 3 D ou t 4 D ou t 5 Do ut 6 D o ut 7
Interrupted by precharge
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 17/46
ESMT
Write Interrupted by a Write
M53D128168A
Operation Temperature Condition -40C~85C
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
CLK CL K 1tCK C OMM AN D N OP WR IT E A WR IT E B N OP NO P N OP NO P N OP N OP 0 1 2 3 4 5 6 7 8
D QS
D Q's tCCD
D in A0
D in A1
Di n B0
D in B 1
Di n B2
D in B3
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 18/46
ESMT
Write Interrupted by a Read & DM
M53D128168A
Operation Temperature Condition -40C~85C
A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.

CLK CLK
0
1
2
3
4
5
6
7
8
COMMAND
NOP
W RITE
NOP tDQSS(max)
NOP
NOP tCDLR
READ
NOP
NOP
NOP
DQS
Hi-Z tWPRES
5)
DQ's
H i- Z
Dina0 Dina1 Dina2 Dina3 Dina4 D ina5 Dina6 Dina7
Dout0 Dout1
DM tDQSS(min) DQS Hi-Z tWPRES DQ's Hi-Z
5)
tCDLR
Dina0 Dina1 D ina2 Dina3 Dina4 Dina5 Dina6 D ina7
Dout0 Dout1
DM
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation. 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM. 5. It is illegal for a Read command interrupt a Write with autoprecharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 19/46
ESMT
Write Interrupted by a Precharge & DM
M53D128168A
Operation Temperature Condition -40C~85C
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM.
CLK CLK 0 1 2 3 4 5 6 7 8
CO MMAND
NOP
W RITE A
NOP t DQ SS(max)
NOP
NOP
NOP tWR
PrechargeA
W RITE B
NOP
tDQSS(max) tWPREH
DQS
Hi-Z
tWPREH
tWPRES DQ's H i- Z
Dina0 Dina1 Dina2 Dina3
tWPRES
Dinb0
DM tDQS S(min) DQS Hi-Z tWPRES tWPREH tWPRES tWPREH tWR t DQSS(min)
DQ's
Hi-Z
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
Dinb0 Dinb1
DM
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow "Write recovery" which is the time required by a Mobile DDR SDRAM core to properly store a full "0" or "1" level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 20/46
ESMT
Burst Stop
M53D128168A
Operation Temperature Condition -40C~85C
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation.

0 CLK CLK 1 2 3 4 5 6 7 8
CO MMAND
READ A
Burst Stop
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst read ends after a deley equal to the CAS lantency.
DQS
Hi-Z
DQ's
Hi-Z
D out 0 Dout 1
The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required. 1. 2. 3. 4. 5. 6. The BST command may only be issued on the rising edge of the input clock, CLK. BST is only a valid command during Read burst. BST during a Write burst is undefined and shall not be used. BST applies to all burst lengths. BST is an undefined command during Read with autoprecharge and shall not be used. When terminating a burst Read command, the BST command must be issued LBST ( "BST Latency") clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
Elite Semiconductor Memory Technology Inc.
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ESMT
DM masking
M53D128168A
Operation Temperature Condition -40C~85C
The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
0 1 2 3 4 5 6 7 8
CLK CLK
CO MMAND
WRITE
NOP tDQSS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS tWPRES tWPREH
Hi-Z
DQ's
D ina0 D ina1 D ina2 Dina3 Dina4 Dina5 D ina6 Dina7
Hi-Z
DM
masked by DM=H
Read With Auto Precharge
If a read with auto-precharge command is initiated, the Mobile DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (tRP) has been satisfied

CLK CLK 0 1 2 3 4 5 6 7 8 9 10
CO MMAND
Bank A ACTIVE
NOP
NOP
NOP
Read A Aut o Precharge
NOP
NOP
NOP tRP
NOP
NOP
NOP
Bank can be reactivated at completion of tRP 1)
DQS
Hi-Z
DQ's
Hi-Z
Auto-Precharge starts
Dout 0 Dout 1 Dout 2 Dout 3
Note : At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 22/46
ESMT
Write with Auto Precharge
M53D128168A
Operation Temperature Condition -40C~85C
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).

0 CLK CLK 1 2 3 4 5 6 7 8
COMMAND
Bank A ACTIVE
NOP
W rite A A uto Pr echar ge
NOP
NOP
NOP
NOP
NOP
NOP
DQS
*Bank can be reactivated at completion of tRP
DQ's
DIN 0
DIN 1
DIN 2
DIN 3
tWR
Internal precharge s tar t
tRP
Auto Refresh & Self Refresh Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). A maximum of eight consecutive AUTO REFRSH commands (with tRFCmin) can be posted to any given Mobile DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 m.
CLK CLK
CO MMA ND
PRE
Auto Refr esh
CMD
CKE = High tRP tRFC
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 23/46
ESMT
Self Refresh
M53D128168A
Operation Temperature Condition -40C~85C
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSRD for locking of DLL.
CLK CLK
COMMAND
NOP
Self Ref resh
NOP
NOP
NOP
NOP tXSR(min)
Active
NOP
CKE tIS tIS
Note :
After self refresh exit, input an auto refresh command immediately.
Power Down
The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set in high for at least tPDEX prior to Row active command. Refresh operations cannot be performed during power down mode, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device.
CLK CLK tPDEX CKE tIS tIS tIS tIS
CO MMAND
Precharge
Active
Read
E n t e r P re c h a rg e p o w e r- d o wn mode
Enter Precharge p o w e r -d o wn mode
E n t e r Ac ti v e p o we r- d o wn mode
Enter Active p o w e r -d o wn mo de
Elite Semiconductor Memory Technology Inc.
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ESMT
Functional Truth Table.
Current CS H L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L L L L L H H L L L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add RAS X H H H L L L L X H H H H L L L L X H H H CAS X H H L H H L L X H H L L H H L L X H H L
WE
M53D128168A
Operation Temperature Condition -40C~85C
Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10
Command DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS NOP NOP ILLEGAL*2 ILLEGAL*2
Action
X H L X H L H L X H L H L H L H L X H L H
Bank Active, Latch RA NOP*4 AUTO-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto -precharge Begin Write, Latch CA, Determine Auto -precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 ILLEGAL Bank Active/ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 25/46
ESMT
Current State CS H L L L WRITE RAS X H H H CAS X H H L
WE
M53D128168A
Operation Temperature Condition -40C~85C
Address X X BA BA, CA, A10
Command DESEL NOP Burst Stop READ/READA
Action NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge*3 Bank Active/ILLEGAL*2 Terminal Burst Precharge ILLEGAL ILLEGAL NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL READ*7 ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL Write Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL With DM=High,
X H L H
L L L L L H L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add
WRITE/WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS
READ with AUTO PRECHARGE
L L L L L L H L L
WRITE with AUTO PRECHARGE
L L L L L L
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ESMT
Current State CS H L L PRE-CHARGIN G L L L L L H L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L CAS X H H L H H L L X H H L H H L L X H H L L H H L L
WE
M53D128168A
Operation Temperature Condition -40C~85C
Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add
Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS
Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (ROW Active after tRCD) NOP (ROW Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 WRITE ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
X H L X H L H L X H L X H L H L X H L H L H L H L
Elite Semiconductor Memory Technology Inc.
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ESMT
Current State CS H L L RE-FRESHING L L L L L H L L MODE REGISTER SETTING L L L L L RAS X H H H L L L L X H H H L L L L CAS X H H L H H L L X H H L H H L L
WE
M53D128168A
Operation Temperature Condition -40C~85C
Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add
Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS
Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
X H L X H L H L X H L X H L H L
ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don't Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL of any bank is not idle. 6. Same bank's previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be performed. 7. Refer to "Read with Auto Precharge: for more detailed information. ILLEGAL = Device operation and / or data integrity are not guaranteed.
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ESMT
Current State CKE n-1 H L L SELF-REFRESHING* 1 L L L L H POWER DOWN L L H DEEP POWER DOWN L L H H H ALL BANKS IDLE*2 H H H H L H ANY STATE other than listed above CKE n X H H H H H L X H L X H L H L L L L L L L H CS X H L L L L X X X X X H X X L H L L L L L X RAS X X H H H L X X X X X X X X L X H H H L X X CAS X X H H L X X X X X X X X X L X H H L X X X
WE
M53D128168A
Operation Temperature Condition -40C~85C
Add X X X X X X X X X X X X X X X X X X X X X X INVALID
Action
X X H L X X X X X X X X X X H X H L X X X X
Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down NOP (Maintain Power Down) INVALID Exit Deep Power Down *3 NOP (Maintain Deep Power Down) Refer to Function True Table Enter Self-Refresh Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function True Table
ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don't Care Note : 1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from All Bank Idle state. 3. The Deep Power Down mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 29/46
ESMT
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
M53D128168A
Operation Temperature Condition -40C~85C
tCH tCL tCK
0 CLK CLK HIGH CKE 1 2 3 4 5 6 7 8 9 10 11 12 13
CS
tIS tIH
RAS
CAS
BA0,BA1
BAa
BAa
BAb
A1 0/AP
Ra
ADDR (A0~An)
Ra
Ca
tDQSS
Cb
WE
DQS
Hi-Z
tRPRE tDQSCK
tRPST
Hi-Z
tDQSS
tDSC tDQSL tDQSH tWPREH
Db0 Db1 Db2
tWPST
Hi-Z
tWPRES
Qa0 Qa1 Qa2 Qa3
DQ
Hi-Z
H i-Z
Db3
H i-Z
tAC
DM
tQHS
t D St D H
CO MMA ND
Active
READ
WRITE
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
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ESMT
Multi Bank Interleaving READ (@BL=4, CL=3)
M53D128168A
Operation Temperature Condition -40C~85C
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
BAa
BAb
A 10/AP
Ra
Rb
ADDR (A0~An)
Ra
Rb
Ca
Cb
WE
tRRD
DQS Hi-Z
tCCD
DQs
Hi-Z
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
DM
tRCD
CO MMA ND
ACTIVE ACTIVE READ READ
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ESMT
Multi Bank Interleaving WRITE (@BL=4)
0 CLK CLK 1 2 3 4 5
M53D128168A
Operation Temperature Condition -40C~85C
6
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
BAa
BAb
A10/AP
Ra
Rb
tRRD
ADDR (A0~An)
Ra Rb Ca
tRCD
Cb
WE
DQS
DQ
Da0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
DM
tRCD
CO MMAND
ACTIVE ACTIVE READ READ
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 32/46
ESMT
Read with Auto Precharge (@BL=8)
0 CLK CLK 1 2 3 4 5
M53D128168A
Operation Temperature Condition -40C~85C
6
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
Ra
ADDR (A 0~A n)
Ca
Ra
WE
Auto prechar ge start
tRP
No te DQS(CL=3) Hi-Z
1)
DQ(CL=3)
H i-Z
Qa0
Qa1
Qa2
Qa3
Qa4
Qa 5
Qa6
Qa7
DM
CO MMAND
READ
ACTIVE
Note 1.
The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 33/46
ESMT
Write with Auto Precharge (@BL=8)
M53D128168A
Operation Temperature Condition -40C~85C
CLK CLK
0
1
2
3
4
5
6
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
Ra
ADDR (A0~An)
Ca
Ra
WE
tD AL tWR
DQS
Auto prechar ge s tart
Note1
tRP
DQ
Da0
Da1
Da2
Da3
Da 4
Da5
Da6
Da7
DM
CO MMAND
WRITE
ACTIVE
Note 1.
The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 34/46
ESMT
Read Interrupted by Precharge (@BL=8)
M53D128168A
Operation Temperature Condition -40C~85C
.
0 CLK CLK HIGH CKE 1 2 3 4 5 6 7 8 9 10
CS
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
ADDR (A0~An)
Ca
WE
DQS
Hi-Z 2
tCK
Valid Qa4 Qa5
DQs
Hi-Z
Qa 0
Qa1
Qa2
Qa3
DM
COMMAND
READ
PRE CHARGE
Elite Semiconductor Memory Technology Inc.
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ESMT
Read Interrupted by a Read (@BL=8, CL=3)
0 CLK CLK HIGH 1 2 3 4 5
M53D128168A
Operation Temperature Condition -40C~85C
6
7
8
9
10
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR (A0~An)
Ca
Cb
WE
DQS
Hi-Z
DQs
Hi-Z
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb6
Qb7
DM
CO MMAND
READ
READ
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 36/46
ESMT
Read Interrupted by a Write & Burst stop (@BL=8, CL=3)
0 CLK CLK H IGH 1 2 3 4 5
M53D128168A
Operation Temperature Condition -40C~85C
6
7
8
9
10
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR (A0~An)
Ca
Cb
WE
DQS
Hi-Z
DQs
Hi-Z
Qa0
Qa1
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
DM
CO MMAND
READ
Burst Stop
WRITE
Elite Semiconductor Memory Technology Inc.
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ESMT
Write followed by Precharge (@BL=4)
0 CLK CLK 1 2 3 4 5 6
M53D128168A
Operation Temperature Condition -40C~85C
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
A1 0 / A P
ADDR (A0~ An)
Ca
WE
tWR
DQS
DQ
Da0
Da1
Da2
Da3
DM
COMMAND
WRITE
PRE CHARGE
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 38/46
ESMT
Write Interrupted by Precharge & DM (@BL=8)
0 CLK CLK 1 2 3 4 0
M53D128168A
Operation Temperature Condition -40C~85C
1
2
3
4
5
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
BAb
BAc
A10/AP
ADDR (A0~An)
Ca
Cb
Cc
WE
DQS
DQ
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Dc0
Dc1
Dc2
Dc3
DM
tWR
CO MMAND
WRITE
PRE CHARGE
tCCD
WRITE WRITE
Elite Semiconductor Memory Technology Inc.
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ESMT
Write Interrupted by a Read (@BL=8, CL=3)
0 CLK CLK 1 2 3 4 5
M53D128168A
Operation Temperature Condition -40C~85C
6
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR (A0~An)
Ca
Cb
WE
DQS
Hi- Z
DQ
Hi-Z
Da0
Da1
Da2
Da3
Da4
Da5
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Maskecd by DM
DM
tCDLR
CO MMAND
WRITE READ
Elite Semiconductor Memory Technology Inc.
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ESMT
DM Function (@BL=8) only for write
0 CLK CLK HIG H 1 2 3 4 5 6
M53D128168A
Operation Temperature Condition -40C~85C
7
8
9
10
CKE
CS
RAS
CAS
BA0,BA1
BAa
A10/AP
ADDR (A0~An)
Ca
WE
DQS(CL=3)
DQ(CL=3)
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
DM
CO MMAND
WRITE
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 41/46
ESMT
Deep Power Down Mode Entry & Exit Cycle
M53D128168A
Operation Temperature Condition -40C~85C
Note : DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM : Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the device exits from Deep Power Down Mode. TO ENTER DEEP POWER DOWN MODE 1) 2) 3) The deep power down mode is entered by having CS and held low with RAS and CAS high at the rising edge of the clock. While CKE is low. Clock must be stable before exited deep power down mode. Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE 4) The deep power down mode is exited by asserting CKE high. 5) In case of 2/CS, 2CKE device with 2/CS & 2CKE, 200s wait tine is required even if only 1 device exits from Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence. Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 42/46
ESMT
Mode Register Set
0 CLK CLK HIGH 1 2 3 4 5 6 7 8 9 10 11
M53D128168A
Operation Temperature Condition -40C~85C
12
13
14
15
16
17
18
19
CKE
CS
RAS
CAS
WE
BA0,BA1
KEY
A10/AP ADDRESS KEY ADDR (A0~An) DQS
KEY
KEY
Hi-Z
tRP
tMRD
Hi-Z
DQs
DM
CO MMA ND
Precharge Command All Bank MRS Co mmand
Any Command
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 43/46
ESMT
PACKING 60-BALL DIMENSIONS DDR SDRAM ( 8x13 mm )
M53D128168A
Operation Temperature Condition -40C~85C
Symbol A A1 A2 b D E D1 E1 e e1
Dimension in mm Min Norm Max 1.20 0.30 0.35 0.40 0.80 0.40 0.45 0.50 7.90 8.00 8.10 12.90 13.00 13.10 6.40 11.0 0.80 1.00
Dimension in inch Min Norm Max 0.047 0.012 0.014 0.016 0.031 0.016 0.018 0.020 0.311 0.315 0.319 0.508 0.512 0.516 0.252 0.433 0.031 0.039
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 44/46
ESMT
Revision History
Revision 1.0 Date 2008.12.31 Original
M53D128168A
Operation Temperature Condition -40C~85C
Description
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 45/46
ESMT
Important Notice All rights reserved.
M53D128168A
Operation Temperature Condition -40C~85C
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008 Revision : 1.0 46/46

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